ML9042 View Datasheet(PDF) - LAPIS Semiconductor Co., Ltd.
Part Name
Description
MFG CO.
'ML9042' PDF : 58 Pages View PDF
LAPIS Semiconductor
FEDL9042-01
ML9042-xx
N ABE
00
01
10
11
Number of
display lines
1
1
2
2
Font size
58
58
58
58
Duty
1/8
1/9
1/16
1/17
Number of
biases
4
4
5
5
Number of
common signals
8
9
16
17
Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270
kHz.
7) CGRAM Address Setting
Instruction code:
RS1 RS0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
0
1
C5
C4
C3
C2
C1
C0
This instruction sets the CGRAM address to the data represented by the bits C5 to C0 (binary).
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the CGRAM address bits C5 to
C0 set in the instruction code at that time.
Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
8) DDRAM Address Setting
Instruction code:
RS1 RS0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
1
D6
D5
D4
D3
D2
D1
D0
This instruction sets the DDRAM address to the data represented by the bits D6 to D0 (binary).
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.
The CPU writes or reads character codes starting from the one represented by the DDRAM address bits D6 to
D0 set in the instruction code at that time.
In the 1-line mode (the “N” bit is “0”), the DDRAM address represented by bits D6 to D0 (binary) should be in
the range “00” to “4F” in hexadecimal.
In the 2-line mode (the “N” bit is “1”), the DDRAM address represented by bits D6 to D0 (binary) should be in
the range “00” to “27” or “40” to “67” in hexadecimal.
If an address other than above is input, the ML9042 cannot properly write a character code in or read it from the
DDRAM.
Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
9) DDRAM/ABRAM/CGRAM Data Write
RS1
RS0
R/W DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Instruction code:
1
1
0
E7
E6
E5
E4
E3
E2
E1
E0
A character code (E7 to E0) is written to the DDRAM, Display-ON data (E7 to E0) to the ABRAM or a character
pattern (E7 to E0) to the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is written, the address counter (ADC) is incremented or decremented as set by the Entry Mode
Setting instruction (see 3).
Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
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