MP7610
ELECTRICAL CHARACTERISTICS (CONT’D)
Parameter
DYNAMIC PERFORMANCE
Voltage Settling from LD
to VDAC Out1
Channel-to-Channel Crosstalk6
Digital Feedthrough1, 6
Power Supply Rejection Ratio
REFERENCE INPUTS
Impedance of VREF
VREF Voltage1, 2
DIGITAL INPUTS3
Logic High
Logic Low
Input Current
Input Capacitance1
ANALOG OUTPUTS
Output Swing
Output Drive Current
Output Impedance
Output Short Circuit Current
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
POWER SUPPLIES
VCC Voltage5
VEE Voltage5
DVDD Voltage
Positive Supply Current
Negative Supply Current
Digital Supply Current
Power Dissipation
ANALOG GROUND CURRENT
Per Channel1
DIGITAL TIMING
SPECIFICATIONS1,4
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
DAC Register Load Pulse Width
Preset Pulse Width
Clock Edge to Load Time
LD Falling Edge to SDO
Tri-state Enable
25°C
Tmin to Tmax
Symbol Min Typ Max
Min Max Units
tsd
CT
Q
PSRR
30
50
0.04
--70
5
50 ms
LSB
dB
ppm/%
REF
VREF
350 700 1.05k
3.5
6
VIH
2.4
VIL
0.8
IL
±10
CL
8
--VEE +1.4 VCC --1.4
--5
5
RO
1
ISC
25
30
40
55
350 1.05k W
V
V
V
mA
pF
V
mA
W
mA
mA
mA
mA
VOH
4.5
V
VOL
0.5
V
VCC VREF+1.5 12 12.75 VREF+1.5 12.75 V
VEE --12.75 --12
--5 --12.75
--5 V
DVDD
4.5
5 5.5
4.5
5.5 V
ICC
8
10
10 mA
IEE
15
20
20 mA
IDD
2
2 mA
PDISS
320 420
450 mW
IAGND
±60
mA
tCH, tCL
60
ns
tDS
15
ns
tDH
15
ns
tPD
40
ns
tLD
45
ns
tPR
65
ns
tCKLD1
140
ns
tCKLD2
0
tHZ1
50
ns
Test Conditions/Comments
ZS to FS (20 V Step)
5k, 50pF load
DC
CLK and Data to VOUTi
DVEE & DVCC = ±5%, ppm of FS
See Application Hints for Driving
the reference input
+FS to AGND
+FS to VEE
--FS to AGND
--FS to VCC
Bipolar zero
Bipolar zero
Bipolar zero
Bipolar zero
See Application Notes
VIL = 0, VIH = 5.0, CL = 20 pF
Note: tLD and tCKLD2 cannot both
be min. since tCKLD1=tCKLD2+tLD
Rev. 4.01
5