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MP7610AS View Datasheet(PDF) - Exar Corporation

Part Name
Description
MFG CO.
'MP7610AS' PDF : 16 Pages View PDF
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MP7610
SDI 1
(Data In) 0
CLK
1
0
LD 1
0
SDO
1
0
MSB
A3
A2
A1
A0 D13
D12 D11
D10 D9
D8
Previous Data
D0
DAC Register
Loaded
A3 (1)
VOUT
Note:
(1) Because A3 is available immediately after 18th clock edge of DATA Shift-in, only 17 clock cycles are
needed to complete the readback.
Figure 1. Serial Data Timing and Loading
SDI 1
0
SDO 1
0
CLK
1
0
LD 1
0
VOUT+--FFSS
Note:
tDS
tDH
tCH
tPD
tCL
tCKLD2
tHZ1
tLDSU
tHZ2
HIGH Z
tLDCK2
tCKLD1
tLD
tSD
+2 LSB Band
(1) CLK should be high during the falling edge of LD to insure proper function of the shift register.
Figure 2. Serial Data Input Timing (RST = “1”)
RST 1
tPR
0
VOUT
VOUT = 0 V
Note: Reset settling time is <tSD
Figure 3. Reset Operation
Rev. 4.01
7
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