MPC5200B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5200B' PDF : 72 Pages View PDF
PCI CLK
t cyc
t high
t low
0.5 Vcc
0.6 Vcc
0.4 Vcc
0.3 Vcc
0.2 Vcc
Figure 9. PCI CLK Waveform
0.4 Vcc, p-to-p
(minimum)
Sym
tcyc
thigh
t low
—
—
Table 22. PCI CLK Specifications
Description
PCI CLK Cycle Time
PCI CLK High Time
PCI CLK Low Time
PCI CLK Slew Rate
PCI Clock Jitter
(peak to peak)
66 MHz
Min
Max
15
30
6
—
6
—
1.5
4
—
200
33 MHz
Min
Max
30
—
11
—
11
—
1
4
—
200
Units Notes SpecID
ns
ns
ns
V/ns
ps
(1),(3)
—
—
(2)
—
A6.1
A6.2
A6.3
A6.4
—
NOTES:
1. In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending
upon whether the clock frequency is above 33 MHz.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform as shown in Figure 9.
3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.
Table 23. PCI Timing Parameters
Sym
Description
tval
CLK to Signal Valid Delay —
bused signals
tval(ptp) CLK to Signal Valid Delay —
point to point
t on
Float to Active Delay
t off
Active to Float Delay
t su
Input Setup Time to CLK —
bused signals
tsu(ptp) Input Setup Time to CLK — point
to point
th
Input Hold Time from CLK
66 MHz
Min
Max
2
6
2
6
2
—
14
3
—
5
—
0
—
33 MHz
Min
Max
2
11
2
12
2
—
28
7
—
10,12
—
0
—
Units Notes SpecID
ns
(1),(2),(3) A6.5
ns
(1),(2),(3) A6.6
ns
(1)
A6.7
ns
(1)
A6.8
ns
(3),(4)
A6.9
ns
(3),(4)
A6.10
ns
(4)
A6.11
NOTES:
1. See the timing measurement conditions in the PCI Local Bus Specification. It is important that all driven signal transitions drive
to their Voh or Vol level within one Tcyc.
MPC5200B Data Sheet, Rev. 4
22
Freescale Semiconductor
Share Link: 
