CS[0]/CS[3]/DA[2:0]
t1
DIOR/DIOW
WDATA
RDATA
t2
t9
t0
t3 t4
t5
t6
IORDY
tA
tB
Figure 14. PIO Mode Timing
Table 28. Multiword DMA Timing Specifications
Sym
t0
tC
tD
tE
tG
tF
tH
tI
tJ
tKr
tKw
tLr
tLw
Multiword DMA Timing Parameters
Cycle Time
DMACK to DMARQ delay
DIOR/DIOW pulse width (16-bit)
DIOR data access
DIOR/DIOW data setup
DIOR data hold
DIOW data hold
DMACK to DIOR/DIOW setup
DIOR/DIOW to DMACK hold
DIOR negated pulse width
DIOW negated pulse width
DIOR to DMARQ delay
DIOW to DMARQ delay
Min/Max Mode 0(ns) Mode 1(ns)
min
480
150
max
—
—
min
215
80
max
150
60
min
100
30
min
5
5
min
20
15
min
0
0
min
20
5
min
50
50
min
215
50
max
120
40
max
40
40
Mode 2(ns)
120
—
70
50
20
5
10
0
5
25
25
35
35
SpecID
A8.12
A8.13
A8.14
A8.15
A8.16
A8.17
A8.18
A8.19
A8.20
A8.21
A8.22
A8.23
A8.24
MPC5200B Data Sheet, Rev. 4
30
Freescale Semiconductor