MPC5200BDS View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5200BDS' PDF : 72 Pages View PDF
All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers.
This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate
with the drive.
Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency to provide adequate
data transfer rates. Adequate data transfer rates are a function of the following:
• The MPC5200B operating frequency (IP bus clock frequency)
• Internal MPC5200B bus latencies
• Other system load dependent variables
The ATA clock is the same frequency as the IP bus clock in MPC5200B. See the MPC5200B User’s Manual (MPC5200B).
NOTE
All output timing numbers are specified for nominal 50 pF loads.
Table 27. PIO Mode Timing Specifications
Sym
PIO Timing Parameter
Min/Max Mode 0
(ns)
(ns)
Mode 1
(ns)
Mode 2
(ns)
Mode 3
(ns)
Mode 4
(ns)
SpecID
t0
Cycle Time
min
t1 Address valid to DIOR/DIOW setup min
t2
DIOR/DIOW pulse width 16-bit
min
8-bit
min
t2i
DIOR/DIOW recovery time
min
t3
DIOW data setup
min
t4
DIOW data hold
min
t5
DIOR data setup
min
t6
DIOR data hold
min
t9
DIOR/DIOW to address
min
valid hold
tA
IORDY setup
max
tB
IORDY pulse width
max
600
70
165
290
—
60
30
50
5
20
35
1250
383
50
125
290
—
45
20
35
5
15
35
1250
240
30
100
290
—
30
15
20
5
10
35
1250
180
30
80
80
70
30
10
20
5
10
35
1250
120
A8.1
25
A8.2
70
A8.3
70
25
A8.4
20
A8.5
10
A8.6
20
A8.7
5
A8.8
10
A8.9
35
1250
A8.10
A8.11
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
29
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