Electrical Characteristics
3.13.7 eMIOS (MTS)Timing
Table 25. MTS Timing1
Num
Characteristic
Symbol Min
Max Unit
1 eMIOS (MTS) Input Pulse Width
tMIPW
4
—
tCYC
2 eMIOS (MTS) Output Pulse Width
tMOPW
1
—
tCYC
1 MTS timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH, and CL = 50pF with SRC = 0b11.
3.13.8 DSPI Timing
Table 26. DSPI Timing1
Num
Characteristic
Symbol
80 MHz
Min Max
112 MHz
Min Max
132 MHz
Unit
Min
Max
1 SCK Cycle TIme2,3
2 PCS to SCK Delay4
3 After SCK Delay5
4 SCK Duty Cycle
tSCK 25ns 2.9ms 17.9ns 2.0ms 15.2ns 1.7ms
—
tCSC
23
—
15
—
13
—
ns
tASC
22
—
14
—
12
—
ns
tSDC tSCK/2 tSCK/2
—
—
—
–2ns + 2ns
—
ns
5 Slave Access Time
(SS active to SOUT driven)
tA
—
25
—
25
—
25
ns
6 Slave SOUT Disable Time
(SS inactive to SOUT High-Z or
invalid)
tDIS
—
25
—
25
—
25
ns
7 PCSx to PCSS time
tPCSC
4
—
4
—
4
8 PCSS to PCSx time
tPASC
5
—
5
—
5
9 Data Setup Time for Inputs
Master (MTFE = 0)
tSUI
20
—
20
—
20
Slave
Master (MTFE = 1, CPHA = 0)6
2
—
2
—
2
–4
—
3
—
6
Master (MTFE = 1, CPHA = 1)
20
—
20
—
20
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
10 Data Hold Time for Inputs
Master (MTFE = 0)
tHI
–4
—
–4
—
–4
Slave
Master (MTFE = 1, CPHA = 0)6
7
—
7
—
7
21
—
14
—
12
Master (MTFE = 1, CPHA = 1)
–4
—
–4
—
–4
—
ns
—
ns
—
ns
—
ns
MPC5567 Microcontroller Data Sheet, Rev. 0
38
Preliminary—Subject to Change Without Notice
Freescale Semiconductor