MPC5567 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5567' PDF : 56 Pages View PDF
Electrical Characteristics
Table 26. DSPI Timing1 (continued)
Num
Characteristic
Symbol
80 MHz
Min Max
112 MHz
Min Max
132 MHz
Unit
Min
Max
11 Data Valid (after SCK edge)
Master (MTFE = 0)
tSUO
—
5
—
5
—
Slave
—
25
—
25
—
Master (MTFE = 1, CPHA=0)
—
18
—
14
—
Master (MTFE = 1, CPHA=1)
—
5
—
5
—
5
ns
25
ns
13
ns
5
ns
12 Data Hold Time for Outputs
Master (MTFE = 0)
tHO
–5
—
–5
—
–5
—
ns
Slave
5.5
—
5.5
—
5.5
—
ns
Master (MTFE = 1, CPHA = 0)
8
—
4
—
3
—
ns
Master (MTFE = 1, CPHA = 1)
–5
—
–5
—
–5
—
ns
1 DSPI timing specified at VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH,
and CL = 50pF with SRC = 0b11.
2 The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two MPC55xx devices communicating over a DSPI link.
3 The actual minimum SCK Cycle Time is limited by pad performance.
4 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]
5 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
6 This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.
2
3
PCSx
4
1
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
SIN
First Data
Data
Last Data
SOUT
First Data
12
Data
11
Last Data
Figure 18. DSPI Classic SPI Timing — Master, CPHA = 0
MPC5567 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
39
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