MPC5607B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5607B' PDF : 110 Pages View PDF
Electrical characteristics
Table 13. Recommended operating conditions (5.0 V) (continued)
Symbol
Parameter
Conditions
Value
Unit
Min
Max
VDD_BV4 SR Voltage on VDD_BV pin (regulator supply) with
—
4.5
respect to ground (VSS)
Voltage drop2
3.0
5.5
V
5.5
Relative to VDD 3.0 VDD + 0.1
VSS_ADC
VDD_ADC5
SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1
—
(ADC reference) pin with respect to ground (VSS)
SR Voltage on VDD_HV_ADC0, VDD_HV_ADC1
(ADC reference) with respect to ground (VSS)
—
Voltage drop2
VSS 0.1 VSS + 0.1 V
4.5
5.5
V
3.0
5.5
VIN
IINJPAD
Relative to VDD VDD 0.1 VDD + 0.1
SR Voltage on any GPIO pin with respect to ground
—
VSS 0.1
—
V
(VSS)
Relative to VDD
—
VDD + 0.1
SR Injected input current on any pin during overload
—
condition
5
5
mA
IINJSUM SR Absolute sum of all injected input currents during
—
overload condition
50
50
TVDD
SR VDD slope to ensure correct power up6
TA C-Grade Part SR Ambient temperature under bias
—
—
fCPU < 64 MHz7 40
0.25 V/µs
85
°C
TJ C-Grade Part SR Junction temperature under bias
TA V-Grade Part SR Ambient temperature under bias
—
40
110
fCPU < 64 MHz7 40
105
TJ V-Grade Part SR Junction temperature under bias
TA M-Grade Part SR Ambient temperature under bias
—
40
130
fCPU < 64 MHz7 40
125
TJ M-Grade Part SR Junction temperature under bias
—
40
150
1 100 nF capacitance needs to be provided between each VDD/VSS pair.
2 Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
3 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
4 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). While the supply voltage ramps up, the slope on VDD_BV should
be less than 0.9VDD_HV in order to ensure the device does not enter regulator bypass mode.
5 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
6 Guaranteed by device validation. Please refer to Section 4.5.1, “External ballast resistor recommendations for
minimum VDD slope to be guaranteed to ensure correct power up in case of external resistor usage.
7 This frequency includes the 4% frequency modulation guardband.
NOTE
RAM data retention is guaranteed with VDD_LV not below 1.08 V.
MPC5607B Microcontroller Data Sheet, Rev. 6
38
Freescale Semiconductor
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