RESET Initialization
5 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8349E.
5.1 RESET DC Electrical Characteristics
Table 8 provides the DC electrical characteristics for the RESET pins of the MPC8349E.
Table 8. RESET Pins DC Electrical Characteristics1
Characteristic
Symbol
Condition
Input high voltage
VIH
Input low voltage
VIL
Input current
Output high voltage2
IIN
VOH
IOH = –8.0 mA
Output low voltage
VOL
IOL = 8.0 mA
Output low voltage
VOL
IOL = 3.2 mA
Notes:
1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.
2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
Min
2.0
–0.3
2.4
—
—
Max
OVDD + 0.3
0.8
±5
—
0.5
0.4
Unit
V
V
μA
V
V
V
5.2 RESET AC Electrical Characteristics
Table 9 provides the reset initialization AC timing specifications of the MPC8349E.
Table 9. RESET Initialization Timing Specifications
Parameter/Condition
Min
Required assertion time of HRESET or SRESET (input) to
32
activate reset flow
Required assertion time of PORESET with stable clock applied
32
to CLKIN when the MPC8349E is in PCI host mode
Required assertion time of PORESET with stable clock applied
32
to PCI_SYNC_IN when the MPC8349E is in PCI agent mode
HRESET/SRESET assertion (output)
512
HRESET negation to SRESET negation (output)
16
Input setup time for POR configuration signals
4
(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with
respect to negation of PORESET when the MPC8349E is in PCI
host mode
Input setup time for POR configuration signals
4
(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with
respect to negation of PORESET when the MPC8349E is in PCI
agent mode
Max
—
—
—
—
—
—
Unit
tPCI_SYNC_IN
tCLKIN
tPCI_SYNC_IN
tPCI_SYNC_IN
tPCI_SYNC_IN
tCLKIN
—
tPCI_SYNC_IN
Notes
1
2
1
1
1
2
1
MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
13