MPC8349VVAGF View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

MPC8349VVAGF

PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications

Freescale Semiconductor 

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Figure 6 shows the DDR SDRAM output timing diagram for source synchronous mode.

MCK[n]

MCK[n]

tMCK

DDR SDRAM

ADDR/CMD

tDDKHAS, tDDKHCS

tDDKHAX, tDDKHCX

Write A0

NOOP

tDDKHMP

tDDKHMH

MDQS[n]

tDDKHDS

tDDKLDS

tDDKHME

MDQ[x]

D0

D1

tDDKHDX

tDDKLDX

Figure 6. DDR SDRAM Output Timing Diagram for Source Synchronous Mode

Table 16 provides approximate delay information that can be expected for the address and command

signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL.

These numbers are the result of simulations for one topology. The delay numbers will strongly depend on

the topology used. These delay numbers show the total delay for the address and command to arrive at the

DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the

system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup

requirements at the DRAM.

Table 16. Expected Delays for Address/Command

Load

Delay

Unit

4 devices (12 pF)

9 devices (27 pF)

36 devices (108 pF) + 40 pF compensation capacitor

36 devices (108 pF) + 80 pF compensation capacitor

3.0

ns

3.6

ns

5.0

ns

5.2

ns

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

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