MPC8349VVALF View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
MPC8349VVALF
Freescale Semiconductor
'MPC8349VVALF' PDF : 88 Pages View PDF
Clocking
Table 53 provides the operating frequencies for the MPC8349E TBGA under recommended operating
conditions (see Table 2).
Table 53. Operating Frequencies for TBGA
Characteristic1
400 MHz
533 MHz
667 MHz
Unit
e300 core frequency (core_clk)
Coherent system bus frequency (csb_clk)
DDR memory bus frequency (MCK)2
Local bus frequency (LCLKn)3
266–400
100–266
100–133
16.67–133
266–533
100–333
100–133
16.67–133
266–667
100–333
100–166.67
16.67–133
MHz
MHz
MHz
MHz
PCI input frequency (CLKIN or PCI_CLK)
25–66
25–66
25–66
MHz
Security core maximum internal operating frequency
133
133
166
MHz
USB_DR, USB_MPH maximum internal operating
133
133
166
MHz
frequency
1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM]and SCCR[USBMPHCM] must be programmed so that the maximum internal operating
frequency of the security core and USB modules does not exceed the respective values listed in this table.
2 The DDR data rate is 2x the DDR memory bus frequency.
3 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
the csb_clk frequency (depending on RCWL[LBIUCM]).
19.1 System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 54 shows the multiplication factor
encodings for the system PLL.
Table 54. System PLL Multiplication Factors
RCWL[SPMF]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
System PLL Multiplication
Factor
× 16
Reserved
×2
×3
×4
×5
×6
×7
×8
×9
× 10
MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
67
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