MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIPLOGIC DIAGRAM
PECL_CLK
PECL_CLK
0
LVCMOS_CLK
1
LVCMOS_CLK_SEL
(Internal Pulldown)
Pinout: 32-Lead LQFP (Top View)
Q0
16 Q1–Q16
Q17
GNDO
Q5
Q4
Q3
VCCO
Q2
Q1
Q0
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
MPC940L
13
29
12
30
11
31
10
32
9
12345678
VCCO
Q12
Q13
Q14
GNDO
Q15
Q16
Q17
FUNCTION TABLE
LVCMOS_CLK_SEL
Input
0
PECL_CLK
1
LVCMOS_CLK
POWER SUPPLY VOLTAGES
Supply Pin
Voltage Level
VCCI
VCCO
2.5 V or 3.3 V ± 5%
2.5 V or 3.3 V ± 5%
Table 1. Pin Configurations
Pin
PECL_CLK
PECL_CLK
LVCMOS_CLK
LVCMOS_CLK_SEL
Q0–Q17
VCCO
VCCI
GNDO
GNDI
I/O
Input
Input
Input
Output
Type
LVPECL
LVCMOS
LVCMOS
LVCMOS
Supply
Supply
Supply
Supply
Function
Reference Clock Input
Alternative Reference Clock Input
Selects Clock Source
Clock Outputs
Output Positive Power Supply
Core Positive Power Supply
Output Negative Power Supply
Core Negative Power Supply
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
2
MPC940L REV 7 JUNE 5, 2007