MPC940L View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
'MPC940L' PDF : 11 Pages View PDF
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
Pulse
Generator
Z = 50Ω
ZO = 50Ω
MPC940L DUT
ZO = 50Ω
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 1. LVCMOS_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
Differential Pulse
Generator
Z = 50Ω
ZO = 50Ω
MPC940L DUT
ZO = 50Ω
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 2. PECL_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
PCLK_CLK
PCLK_CLK
VPP
Q
tPD
VCMR
VCC
VCC ÷ 2
GND
Figure 3. Propagation Delay (tPD) Test Reference
LVCMOS_CLK
Q
tPD
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
Figure 4. LVCMOS Propagation Delay (tPD)
Test Reference
VCC
VCC ÷ 2
tP
GND
T0
DC = tP/T0 x 100%
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
Figure 5. Output Duty Cycle (DC)
tSK(O)
VCC
VCC ÷ 2
GND
VOH
VCC ÷ 2
GND
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any two similar delay paths
within a single device.
Figure 6. Output-to-Output Skew TSK(O)
VCC = 3.3 V VCC = 2.5 V
2.4
1.8 V
0.55
0.6 V
tF
tR
Figure 7. Output Transition Time Test Reference
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
VCC = 3.3 V VCC = 2.5 V
2.0
1.7 V
0.8
0.7 V
tF
tR
Figure 8. Input Transition Time Test Reference
6
MPC940L REV 7 JUNE 5, 2007
Share Link: 
