MPC9600 Data Sheet
LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
VCCA
VCC
7
CCLK (Pulldown)
0
0
PCLK
PCLK
(Pulldown)
Ref PLL
1
FB
/2
1
/4
/8
REF_SEL
(Pullup) VCC/2
200 – 400 MHz
/12
FB_IN (Pulldown)
FSELA (Pullup)
0
Bank A
DQ
1
FSELB (Pullup)
FSELC (Pullup)
FSEL_FB
OE
(Pullup)
(Pulldown)
0
Bank B
DQ
1
0
Bank C
DQ
1
0
Feedback
DQ
1
8
GND
Figure 1. MPC9600 Logic Diagram
QA0
QA1
QA2
QA3
QA4
QA5
QA6
QB0–6
7
QC0–6
7
QFB
MPC9600 REVISION 6 JANUARY 7, 2013
2
©2013 Integrated Device Technology, Inc.