MSM5718B70-53GS-K View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM5718B70-53GS-K' PDF : 40 Pages View PDF
¡ Semiconductor
MSM5718B70
Serial Mode Packet
Serial Mode Packets are used to instruct the RDRAM to perform a operating mode change. A Serial
Mode Packet is simply a pulse on the BusEnable line.
3tCYCLE
1tCYCLE
19tCYCLE
3tCYCLE
7tCYCLE
Read Request Nack
(Miss)
Read Request Ack
(Hit)
Read Data
Fig. 11 Sample 32-Byte Read Miss and Read Hit Transactions
Bus- Bus-
Enable Ctrl
[0] SMode —
even [0]
[0] SMode —
odd [1]
Time
BusData (8:0)
—
—
Fig. 12 Serial Mode Packet1
Note: 1. A — in this diagram signifies that this pin is not used by this packet. If it is not used
by another packet, it is pulled to a logic zero value.
RDRAM OVERVIEW
The figure on the next page is a block diagram of the RDRAM device. The Rambus channel interface
consists of a clock generator, a receiver, and a transmitter. The clock generator uses the external clock
signals RxClk and TxClk (tapped off the channel traces ClockFromMaster and ClockToMaster) and
creates the internal signals RClk and TClk. These are used by the receiver and transmitter,
respectively, to transfer a bit every 2 nanoseconds on each wire between the RDRAM and the master
device. The receiver and transmitter blocks also contain multiplexing and storage hardware to
permit the internal RDRAM data paths to operate at the slower clock rate (but equivalent bandwidth)
of eight bytes transferred every 15 or 16 nanoseconds (four clock cycles).
The RDRAM also contains control logic and configuration registers. The registers are read and
written using special register space commands and control various aspects of RDRAM operation as
described on page 19.
The remaining logic consists of a standard DRAM memory core and row sense amplifier caches.
13
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