MSM5718B70
¡ Semiconductor
Deviceld Register - 1
Read-write register for setting the base
address of the RDRAM.
876543210
Byte[0]
IdField[35:21]
IdField [35:21] - Compared to Adr[35:21] of
request packet to select RDRAM.
Byte[1]
–
–
Byte[2]
–
–
Byte[3]
–
–
Delay Register -2
Read-write and read-only register to
program the CAS access delays.
876543210
Byte[0]
AckWinDelay AckWinBits AckWinBits - 011 (Number of AckWinDelay bits)
AckWinDelay - Normally set to 101 (5 busclocks)
Byte[1]
ReadDelay ReadBits ReadBits - 011 (Number of ReadDelay bits)
ReadDelay - Normally set to 111 (7 busclocks)
Byte[2]
AckDelay AckBits
AckBits - 010 (Number of AckDelay bits)
AckDelay - Normally set to 011 (3 busclocks)
Byte[3]
WriteDelay WriteBits WriteBits - 011 (Number of WriteDelay bits)
WriteDelay - Normally set to 001 (1 busclocks)
AckWinDelay adjusts the size of the acknowledge window. ReadDelay, WriteDelay, and AckDelay adjust the time
from the end of the packet to the start of read data, write data, and the acknowledge packets, respectively.
Mode Register - 3
87654
Byte[0]
CE X2 PL
3210
AS DE
Read-write register for initializing the RDRAM
and for controlling operating modes.
DE (DevEn) - Selects RDRAM at initialization
AS - Set to one
Byte[1]
C5 C2
Byte[2]
C4 C1
Byte[3]
C3 C0
PL (PwrLng) - Selects powerdown wake-up time
X2 (CCMult) - Set to one.
CE (CCEnable) - Set to one.
–
–
C[5:0] (CCValue) - Specifies IOL • 63 = minimum
0 = maximum
20