MSM82C37B-5VJS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM82C37B-5VJS' PDF : 34 Pages View PDF
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
PIN FUNCTIONS
Symbol Pin Name Input/Output
Function
VCC Power
—
+5 V power supply
GND Ground
—
Ground (0 V) connection.
CLK Clock
CS Chip Select
Input
Input
Control of MSM82C37B-5 internal operations and data transfer
speed.
CS is active-low input signal used for the CPU to select
the MSM82C37B-5 as an I/O device in an idle cycle.
RESET Reset
Input
RESET is active-high asynchrounous input signal used to clear
command, status, request, temporary registers, and first/last F/F,
and to set mask register. The MSM82C37B-5 enters an idle cycle
following a RESET.
READY Ready
Input
The read or write pulse width can be extended to accomodate
slow access memories and I/O devices when this input is
switched to low level. Note this input must not change within
the prescribed set-up/hold time.
HLDA Hold Acknowledge
Input
HLDA is active-high input signal used to indicate that system bus
control has been released when a hold request is recieved by
the CPU.
DREQ0 - DMA Request
DREQ3 0 - 3 Channels
Input
DREQ is asynchronous DMA transfer request input signals.
Although these pins are switched to active-high by reset, they can
be programmed to become active-low. DMA requests are
received in accordance with a prescribed order of priority. DREQ
must be held until DACK becomes active.
DB0 - DB7 Data Bus 0 - 7
IOR I/O Read
IOW I/O Write
Input/Output
Input/Output
Input/Output
DB is bidirectional three-state signals connected to the system
data bus, and which is used as an input/output of MSM82C37B-5
internal registers during idle cycles, and as an output of the eight
higher order bits of transfer addresses during active cycles.
Also used as input and output of transfer data during memory-
memory transfers.
IOR is active-low bidirectional three-state signal used as an input
control signal for CPU reading of MSM82C37B-5 internal
registers during idle cycles, and as an output control signal for
reading I/O device transfer data in writing transfers during active
cycles.
IOW is active-low bidirectional three-state signal used as an input
control signal for CPU writing of MSM82C37B-5 internal registers
during idle cycles, and as an output control signal for writing I/O
device transfer data in writing transfers during active cycles.
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