MSM82C37B-5VJS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM82C37B-5VJS' PDF : 34 Pages View PDF
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Fixed Priority Mode
In fixed priority mode, channel 0 has the highest priority, followed by channels 1, 2, and 3 in that
order.
Rotating Priority Mode
In rotating priority mode, the order of priority is changed so that the channel where the current
DMA transfer has been completed is given lowest priority. This is to prevent any one channel
from monopolizing the system.
The fixed priority is regained immediately after resetting.
Table 1 MSM82C37B-5 Priority Decision Modes
Priority Mode
Fixed
Rotating
Service Terminated Channel
—
CH0
CH1
CH2
CH3
Highest
CH0
CH1
CH2
CH3
CH0
Order of Priority
CH1
for Next DMA
CH2
Lowest
CH3
CH2
CH3
CH0
CH1
CH3
CH0
CH1
CH2
CH0
CH1
CH2
CH3
Compressed Timing
Setting the MSM82C37B-5 to compressed timing mode enables the S3 state used in extension of
the read pulse access time to be omitted (if permitted by system structure) for two or three clock
cycle DMA transfers. If the S3 state is omitted, the read pulse width becomes the same as the
write pulse width with the address updated in S2 and the read or write operation executed in
S4. This mode is disregarded if the transfer is a memory-memory transfer, transfer.
Extended Writing
When this mode is set, the IOW or MEMW signal which normally appears during the S3 state
is obtained during the S2 state, thereby extending the write pulse width. The purpose of this
extended write pulse is to enable the system to accomodate memories and I/O devices where
the access time is slower. Although the pulse width can also be extended by using READY, that
involves the insertion of a SW state to increase the number of states.
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