MT28C3212P2FL-10B View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28C3212P2FL-10B' PDF : 47 Pages View PDF
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Figure 6
BLOCK ERASE Flowchart
Start
Issue ERASE SETUP
Command and
Block Address
Issue BLOCK ERASE
CONFIRM Command
and Block Address
Read Status Register
Bits
NO
SR 7 = 1?
YES
Full Status Register
Check (optional)1
ERASE
SUSPEND Loop
NO
ERASE
SUSPEND?
YES
BUS
OPERATION COMMAND COMMENTS
WRITE
WRITE
ERASE
SETUP
Data = 20h
Block Addr = Address
within block to be erased
WRITE
ERASE
Data = D0h
Block Addr = Address
within block to be erased
READ
Status register data;
toggle OE# or CE# to
update status register.
Standby
Check SR7
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Write FFh after the last BLOCK ERASE operation to
reset the device to read array mode.
BLOCK ERASE
Completed
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
SR1 = 0?
YES
NO ERASE Attempted
on a Locked Block
SR3 = 0?
NO
VPP Range Error
YES
SR5 = 0?
NO
BLOCK ERASE Failed
YES
BLOCK ERASE Passed
BUS
OPERATION COMMAND COMMENTS
Standby
Standby
Check SR1
1 = Detect locked block
Check SR32
1 = Detect VPP block
Standby
Check SR4 and SR5
1 = BLOCK ERASE
command error
Standby
Check SR53
1 = BLOCK ERASE error
NOTE:
1. Full status register check can be done after each block or after a sequence of blocks.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full
status is checked.
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
Share Link: 
