MT28C3212P2FL-10B View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28C3212P2FL-10B' PDF : 47 Pages View PDF
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
F_WP#
0
0
0
1
1
1
DQ1
0
0
1
0
0
1
1
1
Table 10
Block Locking State Transition
DQ0
0
1
1
0
1
0
1
NAME
Unlocked
Locked (Default)
Lock Down
Unlocked
Locked
Lock Down
Disabled
Lock Down
Disabled
ERASE/PROGRAM
ALLOWED
Yes
No
No
Yes
No
Yes
No
LOCK
To [001]
–
–
To [101]
–
To [111]
–
UNLOCK
–
To [000]
–
–
To [100]
–
To [110]
LOCK
DOWN
To [011]
To [011]
–
To [111]
To [111]
To [111]
–
alone. A locked or unlocked block can be locked down
by writing the lock down command sequence, 60h fol-
lowed by 2Fh. Locked down blocks revert to the locked
state when the device is reset or powered down.
The LOCK DOWN function is dependent on the
F_WP# input pin. When F_WP# = 0, blocks in lock down
[011] are protected from program, erase, and lock sta-
tus changes. When F_WP# = 1, the LOCK DOWN func-
tion is disabled ([111]) and locked down blocks can be
individually unlocked by a software command to the
[110] state, where they can be erased and programmed.
These blocks can then be relocked [111] and unlocked
[110], as desired, as long as F_WP# remains HIGH.
When F_WP# goes LOW, blocks that were previously
locked down return to the lock down state [011] regard-
less of any changes made while F_WP# was HIGH. De-
vice reset or power-down resets all locks, including
those in lock down, to the locked state (see Table 10).
READING A BLOCK’S LOCK STATUS
The lock status of every block can be read in the
read device identification mode. To enter this mode,
write 90h to the bank containing address 00h. Subse-
quent READs at block address +00002 will output the
lock status of that block. The lowest two output pins,
DQ0 and DQ1, represent the lock status. DQ0 indicates
the block lock/unlock status and is set by the LOCK
command and cleared by the UNLOCK command. It is
also automatically set when entering lock down. DQ1
indicates lock down status and is set by the LOCK
Table 11
Chip Protection Configuration Addressing1
ITEM
Manufacturer Code (x16)
Device Code
Top boot configuration
·· Bottom boot configuration
Block Lock Configuration2
Block is unlocked
· Block is locked
·· Block is locked down
Chip Protection Register Lock
Chip Protection Register 1
Chip Protection Register 2
ADDRESS
00000h
00001h
XX002h
80h
81h–84h
85h–88h
DATA
002Ch
44A2h
44A3h
Lock
DQ0 = 0
DQ0 = 1
DQ1 = 1
PR Lock
Factory Data
User Data
NOTE: 1. Other locations within the configuration address space are reserved by
Micron for future use.
2. “XX” specifies the block address of lock configuration.
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
Share Link: 
