2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
TIMING TEST CONDITIONS
Input pulse levels .................... 0.1V VCC to 0.9V VCC
Input rise and fall times .................................... 5ns
Input timing reference levels ......................... 0.5V
Output timing reference levels ..................... 0.5V
Operating Temperature ............... -40oC to +85oC
SRAM READ CYCLE TIMING
DESCRIPTION
Read cycle time
Address access time
Chip enable to valid output
Output enable to valid output
Byte select to valid output
Chip enable to Low-Z output
Output enable to Low-Z output
Byte select to Low-Z output
Chip enable to High-Z output
Output disable to High-Z output
Byte select disable to High-Z output
Output hold from address change
SYMBOL
tRC
tAA
tCO
tOE
tLB, tUB
tLZ
tOLZ
tLBZ, tUBZ
tHZ
tOHZ
tLBHZ, tUBHZ
tOH
-10/-11
VCC = 1.65V–1.95V VCC = 1.80V–2.20V
MIN
MAX
MIN
MAX
100
85
100
85
100
85
35
35
100
85
0
0
0
0
0
0
0
15
0
15
0
15
0
15
0
15
0
15
5
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SRAM WRITE CYCLE TIMING
DESCRIPTION
Write cycle time
Chip enable to end of write
Address valid to end of write
Byte select to end of write
Address setup time
Write pulse width
Write recovery time
Write to High-Z output
Data to write time overlap
Data hold from write time
End write to Low-Z output
SYMBOL
tWC
tCW
tAW
tLBW, tUBW
tAS
tWP
tWR
tWHZ
tDW
tDH
tOW
-10/-11
VCC = 1.65V–1.95V VCC = 1.80V–2.20V
MIN
MAX
MIN
MAX
100
85
100
85
100
85
100
85
0
0
50
50
0
0
0
15
0
15
50
50
0
0
0
0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.