MT28F128J3FS-12F View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28F128J3FS-12F' PDF : 52 Pages View PDF
Figure 7
BLOCK ERASE Flowchart
Start
Issue Single BLOCK
ERASE Command 20h,
Block Address
Write Confirm D0h
Block Address
Read Status
Register
No
SR7 =
1
Full Status
Check if Desired
Erase Flash
Block(s) Complete
Suspend
No
Erase Loop
Suspend Erase
Yes
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
BUS
OPERATION COMMAND COMMENTS
WRITE
ERASE
BLOCK
Data = 20h
Addr = Block Address
WRITE
ERASE
Data = D0h
CONFIRMED Addr = Block Address
READ
Status register data with
the device enabled; OE#
LOW updates SR
Addr = X
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
The erase confirm byte must follow erase setup.
This device does not support erase queuing.
Full status check can be done after all erase and write
sequences complete. Write FFh after the last operation to
reset the device to read array mode.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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