MT28F128J3FS-12F View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28F128J3FS-12F' PDF : 52 Pages View PDF
REDUCING OVERSHOOTS AND UNDER-
SHOOTS WHEN USING BUFFERS OR
TRANSCEIVERS
Overshoots and undershoots can sometimes cause
input signals to exceed Flash memory specifications as
faster, high-drive devices such as transceivers or buff-
ers drive input signals to Flash memory devices. Many
buffer/transceiver vendors now carry bus-interface
devices with internal output-damping resistors or
reduced-drive outputs. Internal output-damping
resistors diminish the nominal output drive currents,
while still leaving sufficient drive capability for most
applications. These internal output-damping resistors
help reduce unnecessary overshoots and undershoots
by diminishing output-drive currents. When consider-
ing a buffer/transceiver interface design to Flash, de-
vices with internal output-damping resistors or re-
duced-drive outputs should be used to minimize over-
shoots and undershoots.
VCC, VPEN, RP# TRANSITIONS
If VPEN or VCC falls outside of the specified operating
ranges, or RP# is not set to VIH, block erase, program,
and lock bit configuration are not guaranteed. If RP#
transitions to VIL during block erase, program, or lock
bit configuration, STS (in default mode) will remain
LOW for a maximum time of tPLPH + tPHRH, until the
RESET operation is complete and the device enters
reset/power-down mode. The aborted operation may
leave data partially corrupted after programming, or
partially altered after an erase or lock bit configuration.
Therefore, BLOCK ERASE and LOCK BIT CONFIGURA-
TION commands must be repeated after normal op-
eration is restored. Device power-off or RP# = VIL clears
the status register. The CEL latches commands issued
by system software and is not altered by VPEN or CEx
transitions, or ISM actions. Its state is read array mode
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
upon power-up, upon exiting reset/power-down
mode, or after VCC transitions below VLKO. VCC must be
kept at or above VPEN during VCC transitions.
After block erase, program, or lock bit configuration,
and after VPEN transitions to VPENLK, the CEL must be
placed in read array mode via the READ ARRAY com-
mand if subsequent access to the memory array is de-
sired. During VPEN transitions, VPEN must be kept at or
below VCC.
POWER-UP/DOWN PROTECTION
During power transition, the device itself provides
protection against accidental block erasure, program-
ming, or lock bit configuration. Internal circuitry resets
the CEL to read array mode at power-up. A system
designer must watch out for spurious writes for VCC
voltages above VLKO when VPEN is active. Because WE#
must be LOW and the device enabled (see Table 2) for
a command write, driving WE# to VIH or disabling the
device inhibits WRITEs. The CEL’s two-step command
sequence architecture provides added protection
against data alteration. In-system block lock and un-
lock capability protects the device against inadvertent
programming. The device is disabled when RP# = VIL
regardless of its control inputs. Keeping VPEN below
VPENLK prevents inadvertent data change.
POWER DISSIPATION
Designers must consider battery power consump-
tion not only during device operation, but also for data
retention during system idle time. Flash memory’s
nonvolatility increases usable battery life because data
is retained when system power is removed.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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