MT46V4M32 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT46V4M32' PDF : 66 Pages View PDF
ADVANCE
128Mb: x32
DDR SDRAM
Figure 21
WRITE to READ – Odd Number of Data, Interrupting
T0
CK#
CK
T1 T1n T2 T2n T3
T4
T5 T5n T6 T6n
COMMAND
WRITE
NOP
ADDRESS
Bank a,
Col b
tDQSS (NOM)
DQS
tDQSS
DQ
DI
b
DM
NOP
tWTR
READ
Bank a,
Col n
NOP
CL = 2
NOP
NOP
DI
n
tDQSS (MIN)
DQS
DQ
DM
tDQSS
DI
b
CL = 2
DI
n
tDQSS (MAX)
DQS
tDQSS
DQ
DI
b
DM
CL = 2
DI
n
DON T CARE
TRANSITIONING DATA
NOTE: 1. DI b = data-in for column b.
2. An interrupted burst of 4 is shown; one data element is written.
3. tWTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements).
4. A8 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 was used, DM would not be required at T3-T4n because the READ command would mask the last
four data elements.
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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