MT46V4M32 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT46V4M32' PDF : 66 Pages View PDF
ADVANCE
128Mb: x32
DDR SDRAM
Figure 24
WRITE to PRECHARGE – Odd Number of Data, Interrupting
T0
CK#
CK
T1 T1n T2 T2n T3
T4
T5
T6
COMMAND
WRITE
NOP
ADDRESS
Bank a,
Col b
tDQSS (NOM)
DQS
tDQSS
DQ
DI
b
DM
NOP
NOP
tWR
PRE9
Bank,
(a or all)
NOP
NOP
tRP
tDQSS (MIN)
DQS
DQ
DM
tDQSS
DI
b
tDQSS (MAX)
DQS
tDQSS
DQ
DI
b
DM
DON T CARE
TRANSITIONING DATA
NOTE: 1. DI b = data-in for column b.
2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 4 is shown; one data elements are written.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same bank.
6. A8 is LOW with the WRITE command (auto precharge is disabled).
7. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE
command would mask the last two data elements.
9. PRE = PRECHARGE command.
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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