FUNCTIONAL BLOCK DIAGRAM
4 Meg x 32
ADVANCE
128Mb: x32
DDR SDRAM
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTERS
13
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
REFRESH 12
COUNTER
ROW-
12
ADDRESS
MUX
12
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4096 x 256 x 64)
SENSE AMPLIFIERS
8,192
2
BANK
CONTROL
LOGIC
2
I/O GATING
DM MASK LOGIC
256
(x64)
COLUMN
DECODER
COLUMN-
ADDRESS
7
8
COUNTER/
LATCH
1
CA0
CLK
32
64
READ
LATCH 32
MUX
DATA
DLL
32
DQS
GENERATOR
DRVRS
1
CA0
CA0
DQS
64
4
MASK
WRITE
4
64
FIFO
8
&
DRIVERS
32
64
clk
clk
32
out
in DATA
4
4
4
RCVRS
32
32
32
CLK
INPUT
1
REGISTERS
DQ0 -
DQ31,
DM0 -
DM3
DQS
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.