ADVANCE
128Mb: x32
DDR SDRAM
PIN DESCRIPTIONS (continued)
TQFP PIN NUMBERS SYMBOL
38, 39, 40, 41, 42, 43, 44 NC
87, 88, 90
91
DNU
93
NC/RFU
52
NC (MCL)
2, 8, 14, 22, 59, 67, 73,
79, 86, 95
5, 11, 19, 62, 70, 76,
82, 92, 99
15, 35, 65, 96
16, 46, 66, 85
58
VDDQ
VSSQ
VDD
VSS
VREF
TYPE
–
–
Supply
Supply
Supply
Supply
Supply
DESCRIPTION
No Connect: These pins should be left unconnected.
Do Not Use: Must float to minimize noise.
Reserved for Future Use
No Connect: Not internally connected. Must Connect LOW (for
compatibility with SGRAM devices).
DQ Power Supply: +2.5V ±0.125V. Isolated on the die for
improved noise immunity. 1.8V option
DQ Ground. Isolated on the die for improved noise immunity.
Power Supply: +2.5V ±0.125V.
Ground.
SSTL_2 reference voltage.
NOTE: 1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins
deemed to be of importance.
FBGA BALLOUT
1
2
3
4
5
6
7
8
9
10 11 12
A DQS0 DM0 VSSQ DQ3 DQ2 DQ0 DQ31 DQ29 DQ28 VSSQ DM3 DQS3
B DQ4 VDDQ NC VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ NC VDDQ DQ27
C DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25
D DQ7 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ24
E DQ17 DQ16 VDDQ VSSQ VSS/θ1 VSS/θ1 VSS/θ1 VSS/θ1 VSSQ VDDQ DQ15 DQ14
F DQ19 DQ18 VDDQ VSSQ VSS/θ1 VSS/θ1 VSS/θ1 VSS/θ1 VSSQ VDDQ DQ13 DQ12
G DQS2 DM2 NC VSSQ VSS/θ1 VSS/θ1 VSS/θ1 VSS/θ1 VSSQ NC DM1 DQS1
H DQ21 DQ20 VDDQ VSSQ VSS/θ1 VSS/θ1 VSS/θ1 VSS/θ1 VSSQ VDDQ DQ11 DQ10
J DQ22 DQ23 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ8
K CAS# WE# VDD VSS A10 VDD VDD RFU3 VSS VDD NC
NC
L
RAS# NC
NC BA1 A2 A11 A9
A5
RFU2 CK
CK# DSF/MCL
M CS# NC BA0 A0 A1 A3 A4 A6 A7 A8/AP CKE VREF
NOTE: 1. This package uses 4 DQS lines
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.