MT48LC128M4A2P-75C View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-75C' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Operations
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 11 on
page 23).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the READ on bank n when registered (Figure 13
and Figure 14 on page 25). DQM should be used one clock prior to the WRITE command to
prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 21
on page 30), with the data-out appearing CL later. The last valid WRITE to bank n will be
data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered
(Figure 19 on page 29). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n
will begin when the READ to bank m is registered (Figure 28 on page 35).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE
to bank n will begin when the WRITE to bank m is registered (Figure 29 on page 36).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-
in registered one clock prior to the READ to bank m (Figure 30 on page 36).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE
to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is reg-
istered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE
to bank m (Figure 31 on page 37).
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
41
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