MT48LC128M4A2P-7EITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-7EITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Operations
Figure 23: Terminating a WRITE Burst
T0
T1
T2
CLK
COMMAND
WRITE
BURST
NEXT
TERMINATE COMMAND
ADDRESS
DQ
BANK,
COL n
DIN
n
(ADDRESS)
(DATA)
Note:
Transitioning Data
DQMs are LOW.
Don’t Care
PRECHARGE
The PRECHARGE command shown in Figure 24 is used to deactivate the open row in a
particular bank or the open row in all banks. The bank(s) will be available for a subse-
quent row access some specified time (tRP) after the PRECHARGE command is issued.
Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” After a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
Figure 24: PRECHARGE Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0–A9, A11, A12
A10
BA0, BA1
All Banks
Bank Selected
BANK
ADDRESS
Don’t Care
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
32
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©2000 Micron Technology, Inc. All rights reserved.
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