MT48LC128M4A2P-7EITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-7EITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Operations
Figure 31: WRITE with Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
WRITE - AP
BANK n
NOP
NOP
BANK n
Internal
States
BANK m
Page Active
WRITE with Burst of 4
Page Active
WRITE - AP
NOP
NOP
NOP
BANK m
Interrupt Burst, Write-Back
tWR - BANK n
Precharge
tRP - BANK n
t WR - BANK m
WRITE with Burst of 4
Write-Back
ADDRESS
DQ
BANK n,
COL a
DIN
a
DIN
a+1
DIN
a+2
BANK m,
COL d
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
Note: DQM is LOW.
Transitioning Data
Don’t Care
Table 7:
CKEn - 1
L
L
H
H
Truth Table 2 – CKE
Notes 1–4 apply to entire table; notes appear below
CKEn
L
H
L
H
Current State
Power-down
Self refresh
Clock suspend
Power-down
Self refresh
Clock suspend
All banks idle
All Banks idle
Reading or writing
COMMANDn
X
X
X
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
AUTO REFRESH
WRITE or NOP
See Table 8 on page 38
ACTIONn
Maintain power-down
Maintain self refresh
Maintain clock suspend
Exit power-down
Exit self refresh
Exit clock suspend
Power-down entry
Self refresh entry
Clock suspend entry
Notes
5
6
7
Notes:
1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COM-
MANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the tXSR period. A minimum of two NOP commands must be provided during tXSR
period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
the next command at clock edge n + 1.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
37
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