MT48LC128M4A2P-7ELITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-7ELITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 50: WRITE – Full-Page Burst
T0
CLK
T1
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
T2
tCK
WRITE
DQM/
DQML, DQMH
A0–A9,
A11, A12
tAS tAH
ROW
tAS tAH
A10
ROW
BA0, BA1
tAS tAH
BANK
tCMS tCMH
COLUMN m1
BANK
DQ
tRCD
tDS tDH
DIN m
T3
NOP
T4
NOP
T5
( ( Tn + 1
))
((
))
((
))
((
))
((
))
NOP ( (
))
NOP
((
))
((
))
Tn + 2
Tn + 3
BURST TERM
NOP
((
))
((
))
((
))
((
))
((
))
((
))
tDS tDH
DIN m + 1
tDS tDH
DIN m + 2
tDS tDH
((
))
DIN m + 3 ( (
))
tDS tDH
DIN m - 1
1,024 (x16) locations within same row
2,048 (x8) locations within same row
4,096 (x4) locations within same row
Full-page burst does
not self-terminate.
Can use BURST TERMINATE
command to stop.2, 3
Full page completed
Notes:
1. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
2. tWR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
Don’t Care
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
66
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