MT48LC128M4A2P-7ELITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-7ELITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 51: WRITE – DQM Operation
T0
T1
T2
T3
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
DQM/
DQML, DQMU
A0–A9,
A11, A12
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
DQ
NOP
WRITE
NOP
tCMS tCMH
COLUMN m2
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
tDS tDH
DIN m
tRCD
T4
T5
T6
NOP
NOP
NOP
tDS tDH
DIN m + 2
tDS tDH
DIN m + 3
Notes: 1. For this example, BL = 4.
2. x16: A11 and A12 = “Don’t Care;” x8: A12 = “Don’t Care.”
T7
NOP
DON’T CARE
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
67
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