MT48LC16M4A2TG View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC16M4A2TG' PDF : 55 Pages View PDF
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
subsequent READ command. Once the READ com-
mand is registered, the data inputs will be ignored, and
WRITEs will not be executed. An example is shown in
Figure 17. Data n + 1 is either the last of a burst of two or
the last desired of a longer burst.
Data for a fixed-length WRITE burst may be fol-
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued
Figure 16
Random WRITE Cycles
T0
T1
T2
T3
CLK
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DIN
n
DIN
DIN
a
x
TRANSITIONING DATA
DIN
m
DON’T CARE
Figure 17
WRITE to READ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DIN
n
BANK,
COL b
DIN
n+1
TRANSITIONING DATA
DOUT
b
DOUT
b+1
DON’T CARE
64Mb: x4, x8, x16
SDRAM
tWR after the clock edge at which the last desired input
data element is registered. The auto precharge mode
requires a tWR of at least one clock plus time, regardless
of frequency. In addition, when truncating a WRITE
burst, the DQM signal must be used to mask input data
for the clock edge prior to, and the clock edge coinci-
dent with, the PRECHARGE command. An example is
shown in Figure 18. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
Figure 18
WRITE to PRECHARGE
T0
CLK
tWR @ tCLK ≥ 15ns
DQM
COMMAND
WRITE
T1
T2
T3
T4
NOP
PRECHARGE
t RP
NOP
NOP
ADDRESS
DQ
BANK a,
COL n
DIN
n
BANK
(a or all)
DIN
n+1
t WR
T5
T6
ACTIVE
NOP
BANK a,
ROW
tWR = tCLK < 15ns
DQM
COMMAND
WRITE
NOP
ADDRESS
BANK a,
COL n
DQ
DIN
n
DIN
n+1
t RP
NOP
PRECHARGE
NOP
NOP
BANK
(a or all)
t WR
ACTIVE
BANK a,
ROW
TRANSITIONING DATA
DON’T CARE
NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
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