MT48LC16M4A2TG View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC16M4A2TG' PDF : 55 Pages View PDF
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO
PRECHARGE. Micron SDRAMs support CONCURRENT
AUTO PRECHARGE. Four cases where CONCURRENT
AUTO PRECHARGE occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a READ
64Mb: x4, x8, x16
SDRAM
on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is regis-
tered (Figure 24).
2. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used
two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will
begin when the WRITE to bank m is registered
(Figure 25).
Figure 24
READ With Auto Precharge Interrupted by a READ
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
READ - AP
BANK n
NOP
READ - AP
BANK m
NOP
NOP
BANK n
Internal
States
BANK m
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t RP - BANK n
READ with Burst of 4
NOP
NOP
Idle
tRP - BANK m
Precharge
ADDRESS
DQ
BANK n,
COL a
BANK m,
COL d
CAS Latency = 3 (BANK n)
DOUT
a
DOUT
a+1
DOUT
d
DOUT
d+1
NOTE: DQM is LOW.
CAS Latency = 3 (BANK m)
TRANSITIONING DATA
DON’T CARE
Figure 25
READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ - AP
BANK n
NOP
NOP
BANK n
Page
Active
READ with Burst of 4
Internal
States
BANK m
Page Active
NOP
WRITE - AP
NOP
NOP
BANK m
Interrupt Burst, Precharge
tRP - BANK n
WRITE with Burst of 4
NOP
Idle
t WR - BANK m
Write-Back
ADDRESS
1
DQM
BANK n,
COL a
BANK m,
COL d
DQ
DOUT
DIN
a
d
DIN
d+1
DIN
d+2
DIN
d+3
CAS Latency = 3 (BANK n)
TRANSITIONING DATA
DON’T CARE
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
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