MT48LC32M16A2P-75LITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC32M16A2P-75LITC' PDF : 68 Pages View PDF
Notes
512Mb: x4, x8, x16 SDRAM
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test
biased at 1.4V.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range (0°C ≤ TA ≤ 70°C for commercial; –40°C ≤ TA
≤ 85°C for industrial) is ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be pow-
ered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh require-
ment is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1ns, then the timing is ref-
erenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. Refer
to Micron technical note TN-48-09.
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease in a proportional amount by the amount the
frequency is altered for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for -75 and -7E.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
47
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