MT48LC32M16A2TG-7ELITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC32M16A2TG-7ELITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 39: READ – With Auto Precharge
T0
T1
T2
T3
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
DQM/
DQML, DQMU
A0–A9,
A11, A12
tAS tAH
ROW
NOP
READ
NOP
tCMS tCMH
COLUMN m 2
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
BANK
ENABLE AUTO PRECHARGE
BANK
DQ
tRCD
tRAS
tRC
tAC
tLZ
CAS Latency
T4
T5
T6
T7
NOP
NOP
NOP
NOP
tAC
tOH
DOUT m
tAt C
tOH
DOUT m + 1
tAC
tOH
DOUT m + 2
tRP
tOH
DOUT m + 3
tHZ
Notes: 1. For this example, BL = 4, and CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
T8
ACTIVE
ROW
ROW
BANK
Don’t Care
Undefined
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
55
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