MT48LC32M4A2_02 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC32M4A2_02' PDF : 59 Pages View PDF
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length READ
bursts may be truncated with a BURST TERMINATE com-
128Mb: x4, x8, x16
SDRAM
mand, provided that auto precharge was not activated.
The BURST TERMINATE command should be issued x
cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 12 for each possible CAS
latency; data element n + 3 is the last desired data ele-
ment of a longer burst.
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
NOP
BURST
NOP
TERMINATE
NOP
ADDRESS
BANK,
COL n
X = 1 cycle
DQ
CAS Latency = 2
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
BURST
NOP
TERMINATE
NOP
NOP
ADDRESS
BANK,
COL n
X = 2 cycles
DQ
CAS Latency = 3
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
NOTE: DQM is LOW.
Figure 12
Terminating a READ Burst
DON’T CARE
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
21
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©2001, Micron Technology, Inc.
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