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MT48LC32M4A2_02 View Datasheet(PDF) - Micron Technology

Part Name
Description
MFG CO.
MT48LC32M4A2_02
Micron
Micron Technology Micron
'MT48LC32M4A2_02' PDF : 59 Pages View PDF
128Mb: x4, x8, x16
SDRAM
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO PRECHARGE.
Micron SDRAMs support CONCURRENT AUTO
PRECHARGE. Four cases where CONCURRENT AUTO
PRECHARGE occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a READ
on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is regis-
tered (Figure 24).
2. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used two
clocks prior to the WRITE command to prevent bus
contention. The PRECHARGE to bank n will begin
when the WRITE to bank m is registered (Figure 25).
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
READ - AP
BANK n
NOP
READ - AP
BANK m
NOP
NOP
BANK n
Internal
States
BANK m
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t RP - BANK n
READ with Burst of 4
NOP
NOP
Idle
tRP - BANK m
Precharge
ADDRESS
BANK n,
COL a
BANK m,
COL d
DQ
DOUT
a
DOUT
a+1
DOUT
d
DOUT
d+1
CAS Latency = 3 (BANK n)
NOTE: DQM is LOW.
CAS Latency = 3 (BANK m)
Figure 24
READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ - AP
BANK n
NOP
NOP
Internal
States
BANK n
BANK m
Page
Active
READ with Burst of 4
Page Active
NOP
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Precharge
tRP - BANK n
WRITE with Burst of 4
NOP
Idle
t WR - BANK m
Write-Back
ADDRESS
DQM1
BANK n,
COL a
BANK m,
COL d
DQ
DOUT
DIN
a
d
DIN
d+1
DIN
d+2
DIN
d+3
CAS Latency = 3 (BANK n)
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
DONT CARE
Figure 25
READ With Auto Precharge Interrupted by a WRITE
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 Rev. E; Pub. 1/02
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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