MT48LC4M32B2P-7 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC4M32B2P-7' PDF : 79 Pages View PDF
128Mb: x32 SDRAM
PRECHARGE Operation
Figure 45: Single WRITE Without Auto Precharge
T0
CLK
tCKS tCKH
CKE
Command
tCMS tCMH
ACTIVE
DQM
Address
A10
BA0, BA1
tAS tAH
Row
tAS tAH
Row
tAS tAH
Bank
DQ
T1
tCK
NOP
T2
tCL
tCH
WRITE
tCMS tCMH
Column m
Disable auto precharge
Bank
tDS tDH
DIN
T3
NOP
T4
T5
T6
T7
T8
NOP
PRECHARGE
NOP
ACTIVE
NOP
All banks
Single bank
Bank
Row
Bank
tRCD
tRAS
tRC
tWR
tRP
Don’t Care
Note: 1. For this example, BL = 1 and the WRITE burst is followed by a manual PRECHARGE.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
71
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© 2001 Micron Technology, Inc. All rights reserved.
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