128Mb: x32 SDRAM
Clock Suspend
Figure 50: Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
Internal
clock
Command
READ
NOP
NOP
NOP
NOP
NOP
Address
Bank,
Col n
DQ
DOUT
DOUT
DOUT
DOUT
Don’t Care
Note: 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
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128mb_x32_sdram.pdf - Rev. U 04/13 EN
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