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MT48LC8M32B2B5-7 View Datasheet(PDF) - Micron Technology

Part Name
Description
MFG CO.
MT48LC8M32B2B5-7
Micron
Micron Technology Micron
'MT48LC8M32B2B5-7' PDF : 55 Pages View PDF
PRELIMINARY
256Mb: x32
SDRAM
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
READ command. Once the READ command is regis-
tered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 17.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst.
Data for a fixed-length WRITE burst may be fol-
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued
tWR after the clock edge at which the last desired input
data element is registered. The “two-clock” write-back
requires at least one clock plus time, regardless of fre-
quency, in auto precharge mode. In addition, when
truncating a WRITE burst, the DQM signal must be
Figure 16
Random WRITE Cycles
T0
T1
T2
T3
CLK
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DIN
n
DIN
DIN
a
x
DIN
m
DON’T CARE
Figure 17
WRITE to READ
T0
T1
T2
T3
CLK
T4
T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DIN
n
BANK,
COL b
DIN
n+1
DOUT
b
DOUT
b+1
TRANSITIONING DATA
DON’T CARE
used to mask input data for the clock edge prior to, and
the clock edge coincident with, the PRECHARGE com-
mand. An example is shown in Figure 18. Data n + 1 is
either the last of a burst of two or the last desired of a
longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be
issued until tRP is met. The precharge will actually be-
gin coincident with the clock-edge (T2 in Figure 18) on
a “one-clock” tWR and sometime between the first and
second clock on a “two-clock” tWR (between T2 and T3
in Figure 18.)
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
Figure 18
WRITE to PRECHARGE
T0
T1
T2
T3
CLK
T4
T5
T6
tWR = 1 CLK (tCK > tWR)
DQM
COMMAND
WRITE
t RP
NOP
PRECHARGE
NOP
NOP
ACTIVE
NOP
ADDRESS
DQ
BANK a,
COL n
DIN
n
BANK
(a or all)
DIN
n+1
t WR
BANK a,
ROW
tWR = 2 CLK (when tWR > tCK)
DQM
COMMAND
WRITE
NOP
ADDRESS
BANK a,
COL n
DQ
DIN
n
DIN
n+1
t RP
NOP
PRECHARGE
NOP
NOP
BANK
(a or all)
t WR
ACTIVE
BANK a,
ROW
NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed
length of two.
DON’T CARE
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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