MT48LC8M32B2B5-7 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC8M32B2B5-7' PDF : 55 Pages View PDF
PRELIMINARY
256Mb: x32
SDRAM
TRUTH TABLE 2 – CKE
(Notes: 1-4)
CKEn-1 CKEn
L
L
L
H
H
L
H
H
CURRENT STATE
Power-Down
Self Refresh
Clock Suspend
Power-Down
Self Refresh
Clock Suspend
All Banks Idle
All Banks Idle
Reading or Writing
COMMANDn
X
X
X
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
AUTO REFRESH
VALID
See Truth Table 3
ACTIONn
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
Exit Self Refresh
Exit Clock Suspend
Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
NOTES
5
6
7
NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock
edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met.
COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR
period. A minimum of two NOP commands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next
command at clock edge n + 1.
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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