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MT48V4M32LFFF View Datasheet(PDF) - Micron Technology

Part Name
Description
MFG CO.
MT48V4M32LFFF
Micron
Micron Technology Micron
'MT48V4M32LFFF' PDF : 61 Pages View PDF
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
ALTERNATING BANK WRITE ACCESSES1
T0
CLK
T1
T2
T3
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
DQMU, DQML
A0-A9, A11
tAS tAH
ROW
tCMS tCMH
COLUMN m 2
A10
BA0, BA1
DQ
tAS tAH
ROW
ENABLE AUTO PRECHARGE
tAS tAH
BANK 0
BANK 0
tDS tDH
tDS tDH
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRRD
DIN m
DIN m + 1
T4
T5
T6
T7
T8
ACTIVE
NOP
WRITE
NOP
NOP
ROW
ROW
COLUMN b 2
ENABLE AUTO PRECHARGE
BANK 1
tDS tDH
DIN m + 2
BANK 1
tDS tDH
tDS tDH
DIN m + 3
DIN b
tWR - BANK 0
tDS tDH tDS tDH
DIN b + 1
DIN b + 2
tRP - BANK 0
tRCD - BANK 1
T9
ACTIVE
ROW
ROW
BANK 0
tDS tDH
DIN b + 3
tRCD - BANK 0
tWR - BANK 1
DON’T CARE
TIMING PARAMETERS
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
tCMH
-8
MIN MAX
1
2.5
3
3
8
10
20
1
2.5
1
-10
MIN MAX
1
2.5
3
3
10
12
25
1
2.5
1
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
SYMBOL*
tCMS
tDH
tDS
tRAS
tRC
tRCD
tRP
tRRD
tWR
-8
-10
MIN MAX MIN MAX UNITS
2.5
2.5
ns
1
1
ns
2.5
2.5
ns
48 120,000 50 120,000 ns
80
100
ns
20
20
ns
20
20
ns
20
20
ns
1 CLK +
1 CLK +
7ns
5ns
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
56
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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