MT55L256L36PB-7.5IT View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT55L256L36PB-7.5IT' PDF : 30 Pages View PDF
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
BGA PIN DESCRIPTIONS
x18
4P
4N
2A, 3A, 5A,
6A, 3B, 5B,
2C, 3C, 5C,
6C, 2R, 6R,
2T, 3T, 5T, 6T
5L
3G
–
–
4M
4H
4K
4E
6B
7T
2B
x32/x36
4P
4N
2A, 2C, 2R,
3A, 3B, 3C,
3T, 4T, 5A,
5B, 5C, 5T,
6A, 6C, 6R
5L
5G
3G
3L
4M
4H
4K
4E
6B
7T
2B
SYMBOL TYPE
DESCRIPTION
SA0 Input Synchronous Address Inputs: These inputs are registered and
SA1
must meet the setup and hold times around the rising edge
SA
of CLK.
BWa#
BWb#
BWc#
BWd#
CKE#
R/W#
CLK
CE#
CE2#
ZZ
CE2
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.
For the x32 and x36 versions, BWa# controls DQa’s and DQPa;
BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc;
BWd# controls DQd’s and DQPd. Parity is only available on the x18
and x36 versions.
Input
Synchronous Clock Enable: This active LOW input permits CLK to
propagate throughout the device. When CKE# is HIGH, the
device ignores the CK input and effectively internally extends
the previous CLK cycle. This input must meet the setup and
hold times around the rising edge of CLK.
Input
Read/Write: This input determines the cycle type when ADV/
LD# is lOW and is the only means for determining READs and
WRITEs. READ cycles may not be converted into WRITEs (and
vice versa) other than by loading a new address. A LOW on this
pin permits BYTE WRITE operations must meet the setup and
hold times around the rising edge of CLK. Full bus-width
WRITEs occur if all byte write enables are LOW.
Input
Clock: This signal registers the address, data, chip enable, byte write
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
Input Synchronous Chip Enable: This active LOW input is used to enable
the device. CE# is sampled only when a new external address is
loaded.
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Input
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
Input Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
(continued on next page)
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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