MT55L256L36PB-7.5IT View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT55L256L36PB-7.5IT' PDF : 30 Pages View PDF
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
TRUTH TABLE
(Notes 5-10)
OPERATION
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
CONTINUE DESELECT Cycle
READ Cycle
(Begin Burst)
READ Cycle
(Continue Burst)
NOP/DUMMY READ
(Begin Burst)
DUMMY READ
(Continue Burst)
WRITE Cycle
(Begin Burst)
WRITE Cycle
(Continue Burst)
NOP/WRITE ABORT
(Begin Burst)
WRITE ABORT
(Continue Burst)
IGNORE CLOCK EDGE
(Stall)
SNOOZE MODE
ADDRESS
USED CE# CE2# CE2 ZZ
None H X X L
None X H X L
None X X L L
None X X X L
External L L H L
ADV/
LD# R/W# BWx OE# CKE# CLK D Q NOTES
L X X X L L-H High-Z
L X X X L L-H High-Z
L X X X L L-H High-Z
H X X X L L-H High-Z 1
L H X L L L-H Q
Next X X X L H X X L L L-H Q 1, 11
External L L H L L H X H L L-H High-Z 2
Next X X X L H X X H L L-H High-Z 1, 2,
11
External L L H L L L L X L L-H D
3
Next X X X L H X L X L L-H D 1, 3,
11
None L L H L L L H X L L-H High-Z 2, 3
Next X X X L H X H X L L-H High-Z 1, 2,
3, 11
Current X X X L X X X X H L-H –
4
None X X X H X X X X X X High-Z
NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle
is executed first.
2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation.
A WRITE ABORT means a WRITE command is given, but no operation is performed.
3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off
the output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet an
application’s requirements.
4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it
occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE
CLOCK EDGE cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,
BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.
6. BWa# enables WRITEs to Byte “a” (DQa pins); BWb# enables WRITEs to Byte “b” (DQb pins); BWc# enables WRITEs to
Byte “c” (DQc pins); BWd# enables WRITEs to Byte “d” (DQd pins).
7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
8. Wait states are inserted by setting CKE# HIGH.
9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle.
11. The address counter is incremented for all CONTINUE BURST cycles.
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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