MX29LV004T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is
not required because data is verified automatically by
internal control circuit. Erasure completion can be veri-
fied by DATA polling and toggle bit checking after auto-
matic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle
bit, DATA polling, timing waveform)
Figure 8. AUTOMATIC CHIP ERASE TIMING WAVEFORM
Address
CE
OE
WE
Data
RY/BY
VCC
Erase Command Sequence(last two cycle)
tWC
tAS
2AAh
555h
tAH
tCH
tGHWL
Read Status Data
VA
VA
tWP
tCS
tWPH
tDS tDH
55h
10h
tBUSY
tWHWH2
In
Progress
Complete
tRB
tVCS
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM0732
REV. 1.1, SEP. 19, 2001
29