MX919B View Datasheet(PDF) - MX-COM Inc
Part Name
Description
MFG CO.
'MX919B' PDF : 48 Pages View PDF
4-Level FSK Modem Data Pump
5. Application
Page 30 of 47
MX919B PRELIMINARY INFORMATION
5.1 Transmit Frame Example
The operations needed to transmit a single Frame consisting of Symbol and Frame Sync sequences, and one
each Header, Intermediate and Last blocks are provided below:
1. Ensure that the Control Register has been loaded with a suitable CKDIV value, that the IRQEN and
TX/RX bits of the Mode Register are '1', the RXEYE and PSAVE bits are '0', and the INVSYM bit is set
appropriately.
2. Read the Status Register to ensure that the BFREE bit is '1', then write 6 Symbol Sync bytes (a
preamble) to the Data Block Buffer and a T24S task to the Command Register.
3. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the IBEMPTY bit should be '0'.
4. Write 6 byte Frame Sync to the Data Block Buffer and a T24S task to the Command Register.
5. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the IBEMPTY bit should be '0'.
6. Write 10 Header Block bytes to the Data Block Buffer and a THB task to the Command Register.
7. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the IBEMPTY bit should be '0'.
8. Write 12 Intermediate Block bytes to the Data Block Buffer and a TIB task to the Command Register.
9. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the IBEMPTY bit should be '0'.
10. Write 8 Last Block bytes to the Data Block Buffer and a TLB task to the Command Register.
11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the IBEMPTY bit should be '0'.
12. Wait for another interrupt from the modem, read the Status Register; the IRQ, BFREE and IBEMPTY bits
should be '1'.
Note: The final symbol of the frame will start to appear approximately 2 symbol times after the Status
Register IBEMPTY bit goes to '1'; a further 16 symbol times should be allowed for the symbol to pass
completely through the RRC filter.
Figure 19 and Figure 20 illustrate the host µC routines needed to send a single Frame consisting of Symbol
and Frame Sync patterns, a Header block, and any number of Intermediate blocks and one Last Block. It is
assumed that the Tx Interrupt Service Routine Figure 20 is called when the MX919B IRQ output line goes
low.
©2001 MX•COM, INC.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480170.003
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