4-Level FSK Modem Data Pump
Page 43 of 47
6.1.4 Timing
µC Parallel Interface Timings (see Figure 28 )
tACSL
Address valid to CS low time
tAH
Address hold time
tCSH
CS hold time
tCSHI
CS high time
tCSRWL CS to WR or RD low time
tDHR
tDHW
tDSW
tRHCSL
Read data hold time
Write data hold time
Write data setup time
RD high to CS low time (write)
tRACL
Read access time from CS low
tRARL
Read access time from RD low
tRL
RD low time
tRX
RD high to D0-D7 3 state time
tWHCSL WR high to CS low time (read)
tWL
WR low time
Notes
1
2
2
Min.
0
0
0
6
0
0
0
90
0
200
0
200
MX919B PRELIMINARY INFORMATION
Typ.
Max.
175
145
50
Units
ns
ns
ns
clock cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing Notes:
1. Xtal/Clock cycles at the XTAL/CLOCK pin.
2. With 30pF max to VSS on D0 - D7 pins.
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