N25Q128A23ESF40F View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
N25Q128A23ESF40F
Numonyx -> Micron
'N25Q128A23ESF40F' PDF : 180 Pages View PDF
Volatile and Non Volatile Registers
N25Q128 - 3 V
Table 5. Volatile Configuration Register
Bit
Parameter Value
Description
Note
0000
As '1111'
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
VCR<7:4>
1000
8
Dummy clock
cycle
1001
9
1010
10
1011
11
To optimize instruction execution
(FASTREAD, DOFR,DIOFR,QOFR,
QIOFR, ROTP) according to the frequency
1100
12
1101
13
1110
1111
14
Target on maximum
allowed frequency fc
(108MHz) and to
guarantee backward
compatibility (default)
VCR<3>
XIP
0
Ready to enter XIP mode To make the data on DQ0 during the first
dummy clock NOT “Don’t Care.” For
devices with feature set digit equal to 2 or 4
1
XIP disabled (default) in the part number (Basic XiP), this bit is
always Don't Care"
VCR<2:0>
Reserved
xxx
reserved
Fixed value = 000b
6.3.1
Note:
Dummy clock cycle: VCR bits 7 to 4
The bits from 7 to 4 of the Volatile Configuration Register, as the bits from 15 to 12 of the
Volatile Configuration register, set the dummy clock cycles number after the fast read
instructions (in all the 3 available protocols). The dummy clock cycles number can be set
from 1 up to 15 as described in Table 5.: Volatile Configuration Register, according to
operating frequency (the higher is the operating frequency, the bigger must be the dummy
clock cycle number, according to Table 4.: Maximum allowed frequency (MHz)) to optimize
the fast read instructions performance.
If the dummy clock number is not sufficient for the operating frequency, the memory reads
wrong data.
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